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table of contents general description ............................................................................................................ ............... 1 features ....................................................................................................................... ............................ 1 ordering information ........................................................................................................... ............. 2 block diagram .................................................................................................................. ..................... 3 SSD1332u1r1 cof package dimensions .......................................................................................... 4 SSD1332u1r1 cof pin assignment................................................................................................. .... 5 pin description................................................................................................................ ....................... 7 functional block descriptions.................................................................................................. ... 9 command table .................................................................................................................. .................. 12 command descriptions ........................................................................................................... .......... 14 maximum ratings ................................................................................................................ ................. 16 dc characteristics............................................................................................................. ............... 16 ac characteristics............................................................................................................. ............... 17 application example ............................................................................................................ ............. 21
table of figures figure 1 - block diagram ....................................................................................................... ....................... 3 figure 2 - SSD1332u1r1 cof pin assignment ...................................................................................... ..... 5 figure 3 - oscillator circuit.................................................................................................. .......................... 9 figure 4 - display data read back procedure - insertion of dummy read.................................................... 10 figure 5 - 6800-series mpu parallel interface characteristics .................................................................. .. 18 figure 6 - 8080-series mpu parallel interface characteristics .................................................................. .. 19 figure 7 - serial interface characteristics.................................................................................... ................ 20 figure 8 - application example for SSD1332u1r1 ................................................................................. ... 21 list of tables table 1 - ordering information ................................................................................................. ..................... 2 table 2 - SSD1332u1r1 cof pin assignment ....................................................................................... ..... 6 table 3 - command table (d/c# =0, r/w#(wr#)=0, e (rd#)=1) .............................................................. 12 table 4 - maximum ratings (voltage reference to v ss ) ............................................................................ 16 table 5 - dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = 25 c) ............................................................................................................................. ............... 16 table 6 - ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = 25c.) ...................................................................................................................... ..................... 17 table 7 - 6800-series mpu parallel interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = -30 to 85c) .......................................................................................................................... .......................... 18 table 8 - 8080-series mpu parallel interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = -30 to 85c) .......................................................................................................................... .......................... 19 table 9 - serial interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = -30 to 85c) .................... 20
solomo solomo solomo solomon systech limited n systech limited n systech limited n systech limited semiconductor technical data this document contains information on a new product under definition stage. solomon systech ltd. reserves the right to change o r discontinue this product without notice. copyright ? 2003 solomon systech limited rev 0.23 08/2003 SSD1332 product preview oled/pled segment/common driver with controller cmos general description SSD1332 is a single-chip cmos oled/pled driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. SSD1332 consists of 288 segments (96rgb) and 64 commons. this ic is designed for common cathode type oled panel. SSD1332 displays data directly from its internal 96x64x16 bits graphic data ram (gddram). data/commands are sent from general mcu through the hardware selectable 6800/8000 series compatible parallel interface or serial peripheral interface. SSD1332 has a 256 steps contrast control and 65k color control. features support max. 96rgb x 64 matrix panel power supply: vdd=2.4v - 3.5v vcc=8.0v - 18.0v oled driving output voltage, 16v maximum dc-dc voltage converter segment maximum source current: 200ua common maximum sink current: 50ma embedded 96x64x16 bit sram display buffer 16 step master current control, and 256 step current control for the three color components programmable frame rate graphic acceleration command set (gac) 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface, serial peripheral interface. wide range of operating temperature: -30 to 85 c
solomon rev 0.23 08/2003 SSD1332 2 ordering information table 1 - ordering information ordering part number package form mpq SSD1332u1r1 cof 100
SSD1332 rev 0.23 08/2003 solomon 3 block diagram common drivers (odd) segment drivers common driver s(even) grey scale decoder display timing generator oscillator gddram mcu interface res# cs# d/c# e (rd#) r/w#(wr#) bs2 bs1 bs0 d7 d6 d5 d4 d3 d2 d1 d0 dc-dc voltage converter seg/com oled driving block command decoder v dd v ss v cc v com h v ref v p a v pb v pc i ref . . . . . . . . . . . . . . . . . . . . . . com62 com60 | com2 com0 sa0 sb0 sc0 sa1 sb1 sc1 | sa95 sb95 sc95 cl cls com1 com3 | com61 com63 . . . . . . . . . . . gd r rese fb vbre f vsl vcl figure 1 - block diagram
solomon rev 0.23 08/2003 SSD1332 4 SSD1332u1r1 cof package dimensions solomon SSD1332u1
SSD1332 rev 0.23 08/2003 solomon 5 SSD1332u1r1 cof pin assignment 100 figure 2 - SSD1332u1r1 cof pin assignment
solomon rev 0.23 08/2003 SSD1332 6 table 2 - SSD1332u1r1 cof pin assignment 1332u1r1 cof pin # 1332u1r1 cof pin # 1332u1r1 cof pin # 1332u1r1 cof pin # 1332u1r1 cof pin # 1332u1r1 cof pin # nc 1 nc 32 sc95 73 sc63 169 sc31 265 nc 361 vcc 2 nc 33 sb95 74 sb63 170 sb31 266 nc 362 vcomh 3 nc 34 sa95 75 sa63 171 sa31 267 nc 363 nc 4 com63 35 sc94 76 sc62 172 sc30 268 nc 364 d7 5 com61 36 sb94 77 sb62 173 sb30 269 nc 365 d6 6 com59 37 sa94 78 sa62 174 sa30 270 nc 366 d5 7 com57 38 sa93 79 sc61 175 sc29 271 com0 367 d4 8 com55 39 sb93 80 sb61 176 sb29 272 com2 368 d3 9 com53 40 sc93 81 sa61 177 sa29 273 com4 369 d2 10 com51 41 sc92 82 sc60 178 sc28 274 com6 370 d1 11 com49 42 sb92 83 sb60 179 sb28 275 com8 371 d0 12 com47 43 sa92 84 sa60 180 sa28 276 com10 372 e(rd#) 13 com45 44 sc91 85 sc59 181 sc27 277 com12 373 r/w#(wr#) 14 com43 45 sb91 86 sb59 182 sb27 278 com14 374 d/c# 15 com41 46 sa91 87 sa59 183 sa27 279 com16 375 res 16 com39 47 sc90 88 sc58 184 sc26 280 com18 376 cs# 17 com37 48 sb90 89 sb58 185 sb26 281 com20 377 iref 18 com35 49 sa90 90 sa58 186 sa26 282 com22 378 bs2 19 com33 50 sc89 91 sc57 187 sc25 283 com24 379 bs1 20 com31 51 sb89 92 sb57 188 sb25 284 com26 380 vdd 21 com29 52 sa89 93 sa57 189 sa25 285 com28 381 vp_c 22 com27 53 sc88 94 sc56 190 sc24 286 com30 382 vp_b 23 com25 54 sb88 95 sb56 191 sb24 287 com32 383 vp_a 24 com23 55 sa88 96 sa56 192 sa24 288 com34 384 vbref 25 com21 56 sc87 97 sc55 193 sc23 289 com36 385 rese 26 com19 57 sb87 98 sb55 194 sb23 290 com38 386 fb 27 com17 58 sa87 99 sa55 195 sa23 291 com40 387 vddb 28 com15 59 sc86 100 sc54 196 sc22 292 com42 388 gdr 29 com13 60 sb86 101 sb54 197 sb22 293 com44 389 vss 30 com11 61 sa86 102 sa54 198 sa22 294 com46 390 nc 31 com9 62 sc85 103 sc53 199 sc21 295 com48 391 com7 63 sb85 104 sb53 200 sb21 296 com50 392 com5 64 sa85 105 sa53 201 sa21 297 com52 393 com3 65 sc84 106 sc52 202 sc20 298 com54 394 com1 66 sb84 107 sb52 203 sb20 299 com56 395 nc 67 sa84 108 sa52 204 sa20 300 com58 396 nc 68 sc83 109 sc51 205 sc19 301 com60 397 nc 69 sb83 110 sb51 206 sb19 302 com62 398 nc 70 sa83 111 sa51 207 sa19 303 nc 399 nc 71 sc82 112 sc50 208 sc18 304 nc 400 nc 72 sb82 113 sb50 209 sb18 305 nc 401 sa82 114 sa50 210 sa18 306 sc81 115 sc49 211 sc17 307 sb81 116 sb49 212 sb17 308 sa81 117 sa49 213 sa17 309 sc80 118 sc48 214 sc16 310 sb80 119 sb48 215 sb16 311 sa80 120 sa48 216 sa16 312 sc79 121 sc47 217 sc15 313 sb79 122 sb47 218 sb15 314 sa79 123 sa47 219 sa15 315 sc78 124 sc46 220 sc14 316 sb78 125 sb46 221 sb14 317 sa78 126 sa46 222 sa14 318 sc77 127 sc45 223 sc13 319 sb77 128 sb45 224 sb13 320 sa77 129 sa45 225 sa13 321 sc76 130 sc44 226 sc12 322 sb76 131 sb44 227 sb12 323 sa76 132 sa44 228 sa12 324 sc75 133 sc43 229 sc11 325 sb75 134 sb43 230 sb11 326 sa75 135 sa43 231 sa11 327 sc74 136 sc42 232 sc10 328 sb74 137 sb42 233 sb10 329 sa74 138 sa42 234 sa10 330 sc73 139 sc41 235 sc9 331 sb73 140 sb41 236 sb9 332 sa73 141 sa41 237 sa9 333 sc72 142 sc40 238 sc8 334 sb72 143 sb40 239 sb8 335 sa72 144 sa40 240 sa8 336 sc71 145 sc39 241 sc7 337
SSD1332 rev 0.23 08/2003 solomon 7 pin description bs0, bs1, bs2 these pins are mcu interface selection input. see the following table: 6800-parallel interface (8 bit) 8080-parallel interface (8 bit) serial interface bs0 0 0 0 bs1 0 1 0 bs2 1 1 0 cs# this pin is the chip select input. the chip is enabled for mcu communication only when cs# is pulled low. res# this pin is reset signal input. when the pin is low, initialization of the chip is executed. d/c# this pin is data/command control pin. when the pin is pulled high, the data at d 7 -d 0 is treated as display data. when the pin is pulled low, the data at d 7 -d 0 will be transferred to the command register. for detail relationship to mcu interface signals, please refer to the timing characteristics diagrams. r/w#(wr#) this pin is mcu interface input. when interfacing to a 6800-series microprocessor, this pin will be used as read/write (r/w#) selection input. read mode will be carried out when this pin is pulled high and write mode when low. when 8080 interface mode is selected, this pin will be the write (wr#) input. data write operation is initiated when this pin is pulled low and the chip is selected. when serial interface is selected, this pin e(rd#) must be connected to vss. e (rd#) this pin is mcu interface input. when interfacing to a 6800-series microprocessor, this pin will be used as the enable (e) signal. read/write operation is initiated when this pin is pulled high and the chip is selected. when connecting to an 8080-microprocessor, this pin receives the read (rd#) signal. data read operation is initiated when this pin is pulled low and the chip is selected. when serial interface is selected, this pin e(rd#) must be connected to vss. d 7 -d 0 these pins are 8-bit bi-directional data bus to be connected to the microprocessor?s data bus. v dd power supply pin. this is also the reference for the oled driving voltages. it must be connected to external source. v ss ground. it also acts as a reference for the logic pins. it must be connected to external ground.
solomon rev 0.23 08/2003 SSD1332 8 v cc this is the most positive voltage supply pin of the chip. it is supplied either by external high voltage source or internal booster v ref this pin is the reference for oled driving voltages. it can be either supplied externally or connected to v cc . v pa, v pb, v pc these pins are the driving voltages for oled driving segment pins sa0-sa95, sb0-sb95 and sc0-sc95 respectively. i ref this pin is segment output current reference pin. a resistor should be connected between this pin and v ss . set the current at 10ua. v comh this pin is the input pin for the voltage output high level for com signals. a capacitor should be connected between this pin and v ss . vddb this is power pin. it should be connected to v dd . vssb this is ground pin. it must be connected to external ground. gdr this is used for testing purpose. it should be left open under normal operation. rese this is used for testing purpose. it should be left open under normal operation. vb ref this is used for testing purpose. it should be left open under normal operation. fb this is used for testing purpose. it should be left open under normal operation. com0-com63 these pins provide the common switch signals to the oled panel. these pins are in high impedance state when display is off. sa0-sa95, sb0-sb95, sc0-sc95 these pins provide the oled segment driving signals. these pins are in high impedance state when display is off. the 396 segment pins are divided into 3 groups, sa, sb and sc. each group can have different color settings for color a, b and c.
SSD1332 rev 0.23 08/2003 solomon 9 functional block descriptions oscillator circuit and display time generator divider internal oscillator m u x cl clk dclk internal display clock figure 3 - oscillator circuit this module is an on-chip low power rc oscillator circuitry (figure 3). the oscillator generates the clock for the display timing generator. reset circuit when res# input is low, the chip is initialized with the following status: 1. display is off 2. 64 mux display mode 3. normal segment and display data column address and row address mapping (seg0 mapped to address 00h and com0 mapped to address 00h) 4. shift register data clear in serial interface 5. display start line is set at display ram address 0 6. column address counter is set at 0 7. normal scan direction of the com outputs 8. master contrast control register is set at 16h 9. individual contrast control registers of color a, b, and c are set at 80h command decoder and command interface this module determines whether the input data is interpreted as data or command. data is interpreted based upon the input of the d/c# pin. if d/c# pin is high, data is written to graphic display data ram (gddram). if it is low, the input at d 7 -d 0 is interpreted as a command and it will be decoded and be written to the corresponding command register.
solomon rev 0.23 08/2003 SSD1332 10 mpu parallel 6800-series interface the parallel interface consists of 16 bi-directional data pins (d 0 -d 15 ), r/w#(wr#), d/c#, e (rd#) and cs#. r/w#(wr#) input high indicates a read operation from the graphic display data ram (gddram) or the status register. rw#/(wr#) input low indicates a write operation to display data ram or internal command registers depending on the status of d/c# input. the e(rd#) input serves as data latch signal (clock) when high provided that cs# is low and high respectively. refer to figure 5 of parallel timing characteristics for parallel interface timing diagram of 6800-series microprocessors. in order to match the operating frequency of display ram with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. this is shown in figure 4 below. n+2 n+1 write column address dummy read data read1 r/ w#(wr#) data bus n n e(rd#) data read2 data read3 figure 4 - display data read back procedure - insertion of dummy read mpu parallel 8080-series interface the parallel interface consists of 16 bi-directional data pins (d 0 -d15), e (rd#), r/w#(wr#), d/c# and cs#. the e(rd#) input serves as data read latch signal (clock) when low, provided that cs# is low and high respectively. display data or status register read is controlled by d/c#. r/w#(wr#) input serves as data write latch signal (clock) when high provided that cs# is low and high respectively. display data or command register write is controlled by d/c#. refer to figure 6 of parallel timing characteristics for parallel interface timing diagram of 8080-series microprocessor. similar to 6800-series interface, a dummy read is also required before the first actual display data read. mpu serial interface the serial interface consists of serial clock sck, serial data sda, d/c# and cs#. sda is shifted into an 8-bit shift register on every rising edge of scl in the order of d 7 , d 6 , ... d 0 . d/c# is sampled on every eighth clock and the data byte in the shift register is written to the display data ram or command register in the same clock. graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is 96 x 64 x 16bits. for mechanical flexibility, re-mapping on both segment and common outputs can be selected by software. for vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the ram data to be mapped to the display. current control and voltage control
SSD1332 rev 0.23 08/2003 solomon 11 this block is used to derive the incoming power sources into the different levels of internal use voltage and current. v cc and v dd are external power supplies. v ref is reference voltage, which is used to derive driving voltage for segments and commons. i ref is a reference current source for segment current drivers. segment drivers/common drivers segment drivers deliver 288 current sources to drive oled panel. the driving current can be adjusted from 0 to 200ua with 256 steps. common drivers generate voltage scanning pulse.
solomon rev 0.23 08/2003 SSD1332 12 command table table 3 - command table (d/c# =0, r/w#(wr#)=0, e (rd#)=1) hex command description 15 a[6:0] b[6: 0] set column address second command a[7:0] sets the column start address from 0-95, por=00d. third command b[7:0] sets the column end address from 0-95 por=95d. 75 a[5:0] b[5:0] set row address second command a[6:0]sets the row start address from 0-63, por=00d. third command b[6:0] sets the row end address from 0-63, por=63d. 81 a[7:0] set contrast for color a (segment pins :sa0 ? sa95) double byte command to select 1 out of 256 contrast steps. contrast increases as level increase. por = 80h 82 a[7:0] set contrast for color b (segment pins :sb0 ? sb95) same as above 83 a[7:0] set contrast for color c (segment pins :sc0 ? sc95) same as above 87 a[3:0] master current control set a[3:0] from 0000, 0001? to 1111 to adjust the master current attenuation factor from 1/16, 2/16? to 16/16. por =1111b, for no attenuation. a0 a[7:0] set re-map & data format a[0]=0, horizontal address increment (por) a[0]=1, vertical address increment a[1]=0, column address 0 is mapped to seg0 (por) a[1]=1, column address 131 is mapped to seg0 a[2]=0, reserve a[3]=0, reserve a[4]=0, scan from com 0 to com [n ?1] a[4]=1, scan from com [n-1] to com0. where n is the multiplex ratio. a[5]=0, disable com split odd even (por) a[5]=1, enable com split odd even a[7:6]=00; 256 color format = 01; 65k color format(por) data formats are defined as cccbbbaa for 256 color cccccbbb for 65k color bbbaaaaa
SSD1332 rev 0.23 08/2003 solomon 13 hex command description a1 a[5:0] set display start line set display ram display start line register from 0-63. display start line register is reset to 00h after por. a2 a[5:0] set display offset set vertical scroll by com from 0-63. the value is reset to 00h after por. a4~a7 set display mode a4h=normal display (por) a5h=entire display on, all pixels turn on at gs level 63 a6h=entire display off, all pixels turns off a7h=inverse display a8 a[5:0] set multiplex ratio the next command determines multiplex ratio n from 16mux-64mux, por=63d (64mux) ae~af set display on/off aeh=display off (por) afh=display on b8 a[7:0] --pw1 b[7:0] --pw3 c[7:0] --pw5 d[7:0] --pw7 : : : ae[7:0] --pw61 af[7:0] --pw63 set gray scale table the next 32 bytes of command set the current drive pulse width of gray scale level gs1, gs3, gs5 ?gs63 as below: a[7:0]=pw1, por=1 b[7:0]=pw3, por=5 c[7:0]=pw5, por= 9 : : : ae[7:0]=pw61, por=121 af[7:0]=pw63, por=125 note: gs0 has no current drive. for gs2 gs4?gs62 : pwn = (pwn -1 +pwn +1 )/2 max pulse width is 125 e3 nop command for no operation
solomon rev 0.23 08/2003 SSD1332 14 command descriptions set column address this command specifies column start address and end address of the display data ram. this command also sets the column address pointer to column start address. set row address this command specifies row start address and end address of the display data ram. this command also sets the row address pointer to row start address. set contrast for color a, b, c this command is to set contrast setting of each color a, b and c. the chip has three contrast control circuits for color a, b and c. each contrast circuit has 256 contrast steps from 00h to ffh. the segment output current increases linearly with the increase of contrast step. master current control this command is to adjust the overall display brightness. the chip has 16 steps segment current reduction. the range is form 1/16[0000] to 16/16[1111]. por is no current reduction [1111]. set re-map this command changes the mapping between the display data column address and segment driver, row address and common driver. it allows flexibility in layout during oled module assembly. when a[5] is set as 0, com outputs are in sequential format. when it is set as 1, com outputs are in odd and even mode. see com layouts in figure 1 and 2. set data format this command allows user to set different data formats for 256 color (8-bit) and 65k color (16-bit). set display start line this command is to set display start line register to determine starting address of display ram to be displayed by selecting a value from 0 to 63. set display offset this is a double byte command. the next command specifies the mapping of display start line (it is assumed that com0 is the display start line, display start line register equals to 0) to one of com0-63. for example, to move the com16 towards the com0 direction for 16 lines, the 6-bit data in the second command should be given by 0010000. set display mode this command is used to set normal display, entire display on, entire display off and inverse display. set entire display on forces the entire display to be at ?gs63? regardless of the contents of the display data ram. set entire display off forces the entire display to be at gray level ?gs0? regardless of the contents of the display data ram. normal display will turn the data to on at the corresponding gray level. set multiplex ratio this command switches default 1:64 multiplex mode to any multiplex mode from 16 to 64. set display on/off this command turns the display on or off. when the display is off, the segment and common output are in high impedance state.
SSD1332 rev 0.23 08/2003 solomon 15 set gray scale table this command is used to set the gray scale table for the display. except gs0, which has no pre-charge and current drive, each gs level is programmed by the pulse width of current drive. nop no operation command
solomon rev 0.23 08/2003 SSD1332 16 maximum ratings table 4 - maximum ratings (voltage reference to v ss ) symbol parameter value unit v dd -0.3 to +4 v v cc 0 to 18 v v ref supply voltage 0 to 18 v v comh supply voltage/output voltage 0 to 16 v - seg/com output voltage 0 to 16 v v in input voltage vss-0.3 to vdd+0.3 v t a operating temperature -30 to +85 oc t stg storage temperature range -65 to +150 oc *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description. dc characteristics table 5 - dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = 25 c) symbol parameter test condition min typ max unit v cc operating voltage 7 11 18 v v dd logic supply voltage 2.4 2.7 3.5 v v oh high logic output level iout =100ua, 3.3mhz 0.9*v dd - v dd v v ol low logic output level iout =100ua, 3.3mhz 0 - 0.1*v dd v v ih high logic input level iout =100ua, 3.3mhz 0.8*v dd - v dd v v il low logic input level iout =100ua, 3.3mhz 0 - 0.2*v dd v i sleep sleep mode current vdd=2.7v, display off, no panel attached - - 5 ua i cc vcc supply current vdd=2.7v, display on contrast =ff, no panel attached - 770 - ua i dd v dd supply current vdd=2.7v, display on contrast =ff, no panel attached - 170 - ua contrast = ff - 160 - ua contrast = af 110 contrast = 5f - 60 - i seg segment output current setting vdd=2.7v, vcc=11v, iref=10ua, all one pattern, display on, segment pin under test is connected with a 20k ? resistive load to vcc. contrast = 00 - 0 - dev segment output current uniformity dev = (i seg ? i mid )/i mid i mid = (i max + i min )/2 i s eg [0:395] = segment current at contrast = ff - - 3 % adj. dev adjacent pin output current uniformity (contrast = ff) adj dev = (i[n]-i[n+1]) / (i[n]+i[n+1]) - 2.0 -- % r on_c common output on resistance vdd - vee=11.7v, iout=30ma; - 23 - ? vcc booster output voltage (vcc) vin=3v, l=22uh; r1=500kohm; r2=50kohm; icc = 30ma(soaking) 10 - 12 v pwr booster output power vin=3v, l=22uh; vcc = 10 v ~ 16v - - 400 mw
SSD1332 rev 0.23 08/2003 solomon 17 ac characteristics table 6 - ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = 25c.) symbol parameter test condition min typ max unit f osc oscillation frequency of display timing generator vdd = 2.7v, iref = 12ua - 0.97 - mhz f frm frame frequency for 64 mux mode 96rgb x 64 graphic display mode, display on, internal oscillator enabled - f osc x 1/(d*k*64) - hz d: divide ratio (por =1) k: number of display clocks (por = 125) refer to command table for detail description
solomon rev 0.23 08/2003 SSD1332 18 table 7 - 6800-series mpu parallel interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = -30 to 85c) symbol parameter min typ max unit t cycle clock cycle time 300 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 15 - - ns t dhr read data hold time 20 - - ns t oh output disable time - - 70 ns t acc access time - - 140 ns pw csl chip select low pulse width (read) chip select low pulse width (write) 120 60 - - ns pw csh chip select high pulse width (read) chip select high pulse width (write) 60 60 - - ns t r rise time - - 15 ns t f fall time - - 15 ns d 0 ~d 7 (write) d 0 ~d 7 (read) e cs# r/w# pw csl t r t f t dh w t oh t acc t dhr valid data t dsw valid data t cycle pw csh t ah t as d/c# figure 5 - 6800-series mpu parallel interface characteristics
SSD1332 rev 0.23 08/2003 solomon 19 table 8 - 8080-series mpu parallel interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = -30 to 85c) symbol parameter min typ max unit t cycle clock cycle time 300 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 15 - - ns t dhr read data hold time 20 - - ns t oh output disable time - - 70 ns t acc access time - - 140 ns pw csl chip select low pulse width (read) chip select low pulse width (write) 120 60 - - ns pw csh chip select high pulse width (read) chip select high pulse width (write) 60 60 - - ns t r rise time - - 15 ns t f fall time - - 15 ns figure 6 - 8080-series mpu parallel interface characteristics pw csh pw cs t f t dsw t dhw t oh t acc valid data t dhr valid data t cycl e t ah t a d/c# rd# cs# d 0 ~d 7 (write) d 0 ~d 7 (read) wr# t r
solomon rev 0.23 08/2003 SSD1332 20 table 9 - serial interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = -30 to 85c) symbol parameter min typ max unit t cycle clock cycle time 250 - - ns t as address setup time 150 - - ns t ah address hold time 150 - - ns t css chip select setup time 120 - - ns t csh chip select hold time 60 - - ns t dsw write data setup time 100 - - ns t dhw write data hold time 100 - - ns t clkl clock low time 100 - - ns t clkh clock high time 100 - - ns t r rise time - - 15 ns t f fall time - - 15 ns t ah t as d/c# valid data t dhw t clk t dsw t clkh t cycle t css t csh t f t r sda(d 7 ) cs# sck(d 6 ) d7 sda ( d 7 ) cs# sck ( d 6 ) d6 d5 d4 d3 d2 d1 d0 figure 7 - serial interface characteristics
SSD1332 rev 0.23 08/2003 solomon 21 application example figure 8 - application example for SSD1332u1r1 color oled panel 96rgb x 64 SSD1332u1r1 com62 . . com0 sa0 sb0 sc0 . . . . . . . . . . sa95 sb95 sc95 com1 . . com63 nc v cc v comh nc d7~d0 e rw# dc# res# cs# i ref bs2 bs1 v dd vp_c vp_b vp_a vb ref rese fb vddb gdr v ss nc d7~d0 e rw# dc# res# cs# v ss [gnd] pin connected to mcu interface: d0~d7, e, r/w#, d/c#, res#, cs# pin internally connected to vdd: m/s#, cls pin internally connected to vss: vssb pin internally connected to vcc: vref pin externally connected to vdd: bs2 pin externally connected to vss: bs1 pin floated: vp_c, vp_b, vp_a, vb ref , rese, fb, vddb, gdr c1~c3: 4.7uf voltage at i ref = vcc ? 3v r1 = (voltage at i ref - vss) / i ref = 910k ? r1 c1 c3 c2 the configuration for 6800-parallel interface mode, externally v cc is shown in the following diagram: (v dd = 3.0v, external v cc = 12v, i ref = 10ua)
solomon rev 0.23 08/2003 SSD1332 22 solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation consequential o r incidental damages. ?typical? parameters can and do vary in different applications. all operating parameters, including ?typica ls? must be validated for each customer application by customer?s technical experts. solomon systech does not convey any license under its patent rig hts nor the rights o f others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the solom on systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon systech products for any suc h unintended o r unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was neglig ent regarding the design or manufacture of the part.

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